Darren wrote:The actual speed the chip is running at will be dictated by the clocks on the board.
Yup.
Darren wrote:... however these clocks may again be divided by logic. for example sending a 50Mhz clock through a flip-flop logic gate will output 2 x 25Mhz 'clocks'.
They're not going to put a 150 MHz crystal on a board like that, let alone route that to multiple components (as some need to run in sync) - there are better ways to do that.
In this case the DSP contains a PLL and they can change the speed the DSP runs at from 1/16 x CLK-REF up to 4096/1 x CLK-REF (see datasheet or the bit about the PLL on this page:
http://www.freescale.com/webapp/sps/sit ... e=DSP56367). A 16, 20 or 25 MHz clock seems fairly common.
One of my development boards has an NXP LPC4330 (ARM Cortex-M4) rated to run at up to 204 MHz - it uses a 12 MHz crystal and a PLL to do that. I also have some FPGA dev boards (such as the XuLA-200) and those can easily synthesize a 150-300 MHz clock from the 12 MHz oscillator on the circuit board; of course, comparing the (internal) clock speed of a CPU with that of an FPGA is not a very sensible thing to do.
I have a cheapy signal generator that uses an AD9851 DAC to generate signals - it runs at 180 MHz using its built-in 6X clock multiplier (doesn't state what type) and an external 30 MHz crystal.
Darren wrote:The easiest way to know for sure (without the luxury of a schematic) would be to probe the CLK input line on the chip with an oscilloscope.
In my experience the added capacitance (tens of pF) caused by standard passive probes (even at 10x attenuation) is often enough to stop the clock completely. I think you'd need an active probe to measure a crystal oscillator reliably (and those are rather expensive). I have a Rigol DS1052E scope (hacked to 1102E) and an old analog Philips one.
Anyway, it looks like I'm derailing this tread and turning it into a pissing contest. I'm certainly rapidly reaching the limits of my knowledge about stuff like this.
